CYP RXC User Manual download pdf (Page 5)

CYRF6936

Document #: 38-16015 Rev. *F Page 5 of 39

Frequency Synthesizer

Before transmission or reception may commence, it is

necessary for the frequency synthesizer to settle. The settling

time varies depending on channel; 25 fast channels are

provided with a maximum settling time of 100-µs.

The “fast channels” (<100-µs settling time) are every 3

channel, starting at 0 up to and including 72 (i.e.,

0,3,6,9…….69 & 72).

Baseband and Framer

The baseband and framer blocks provide the DSSS encoding

and decoding, SOP generation and reception and CRC16

generation and checking, as well as EOP detection and length

field.

Packet Buffers and Radio Configuration

Registers

Packet data and configuration registers are accessed through

the SPI interface. All configuration registers are directly

addressed through the address field in the SPI packet (as in

the CYWUSB6934). Configuration registers are provided to

allow configuration of DSSS PN codes, data rate, operating

mode, interrupt masks, interrupt status, etc.

SPI Interface

The CYRF6936 IC has a SPI interface supporting communi-

cations between an application MCU and one or more slave

devices (including the CYRF6936). The SPI interface supports

single-byte and multi-byte serial transfers using either 4-pin or

3-pin interfacing. The SPI communications interface consists

of Slave Select (SS

), Serial Clock (SCK), and Master Out-

Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data

(SDAT).

The SPI communications is as follows:

• Command Direction (bit 7) = “1” enables SPI write trans-

action. A “0” enables SPI read transactions.

• Command Increment (bit 6) = “1” enables SPI auto address

increment. When set, the address field automatically incre-

ments at the end of each data byte in a burst access,

otherwise the same address is accessed.

• Six bits of address.

• Eight bits of data.

The device receives SCK from an application MCU on the SCK

pin. Data from the application MCU is shifted in on the MOSI

pin. Data to the application MCU is shifted out on the MISO

pin. The active-low Slave Select (SS

) pin must be asserted to

initiate an SPI transfer.

The application MCU can initiate SPI data transfers via a multi-

byte transaction. The first byte is the Command/Address byte,

and the following bytes are the data bytes as shown in

Figure 7-1 through Figure 7-4.

The SPI communications interface has a burst mechanism,

where the first byte can be followed by as many data bytes as

desired. A burst transaction is terminated by deasserting the

slave select (SS

= 1).

The SPI communications interface single read and burst read

sequences are shown in Figure 7-2 and Figure 7-3, respec-

tively.

The SPI communications interface single write and burst write

sequences are shown in Figure 7-4 and Figure 7-5, respec-

tively.

This interface may optionally be operated in a 3-pin mode with

the MISO and MOSI functions combined in a single bidirec-

tional data pin (SDAT). When using 3-pin mode, user firmware

should ensure that the MOSI pin on the MCU is in a high-

impedance state except when MOSI is actively transmitting

data.

The device registers may be written to or read from 1 byte at

a time, or several sequential register locations may be

written/read in a single SPI transaction using incrementing

burst mode. In addition to single byte configuration registers,

the device includes register files; register files are FIFOs

written to and read from using non-incrementing burst SPI

transactions.

The IRQ pin function may optionally be multiplexed onto the

MOSI pin; when this option is enabled the IRQ function is not

available while the SS

pin is low. When using this configu-

ration, user firmware should ensure that the MOSI pin on the

MCU is in a high impedance state whenever the SS

pin is high.

The SPI interface is not dependent on the internal 12-MHz

clock, and registers may therefore be read from or written to

while the device is in sleep mode, and the 12-MHz oscillator

disabled.

The SPI interface and the IRQ and RST pins have a separate

voltage reference pin (V

), enabling the device to interface

directly to MCUs operating at voltages below the CYRF6936

IC supply voltage.

Table 7-2. Typical Range Observed Table

Environment Typical Range (meters)

Outdoor 30

Office 20

Home 15

Note: Range observed with CY4636 WirelessUSB LP KBM v1.0 (Keyboard)

1 2 3 4 5 6 7 8 9 10 ... 38 39

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CYP RXC User Manual Page 5

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