CYRF6936
Document #: 38-16015 Rev. *F Page 16 of 39
Mnemonic RX_CFG_ADR
Address 0x06
Bit 7 6 5 4 3 2 1 0
Default 1 0 0 1 0 - 1 0
Read/Write R/W R/W R/W R/W R/W - R/W R/W
Function AGC EN LNA ATT HILO FAST TURN
EN
Not Used RXOW EN VLD EN
Status bits are non-atomic (different flags may change value at different times in response to a single event).
Bit 7 Automatic Gain Control (AGC) Enable. When this bit is set, AGC is enabled, and the LNA is controlled by the AGC circuit.
When this bit is cleared the LNA is controlled manually using the LNA bit. Typical applications will clear this bit during initializa-
tion. It is recommended that this bit be cleared and bit 6 (LNA) be set unless the device will be used in a system where it may
receive data from a device using an external PA to transmit signals at >+4 dBm.
Bit 6 Low Noise Amplifier (LNA) Manual Control. When AGC EN (Bit 7) is cleared, this bit controls the state of the receiver LNA;
when AGC EN is set, this bit has no effect. Setting this bit enables the LNA; clearing this bit disables the LNA. Device current in
receive mode is slightly lower when the LNA is disabled. Typical applications will set this bit during initialization.
Bit 5 Receive Attenuator Enable. Setting this bit enables the receiver attenuator. The receiver attenuator may be used to de-sensi-
tize the receiver so that only very strong signals may be received. This bit should only be set when the AGC EN is disabled and
the LNA is manually disabled.
Bit 4 HILO. When FAST TURN EN is set, this bit is used to select whether the device will use the high frequency for the channel
selected, or the low frequency. 1 = hi; 0 = lo. When FAST TURN EN is not enabled this also controls the highlow bit to the
receiver and should be left at the default value of 1 for high side receive injection. Typical applications will clear this bit during
initialization.
Bit 3 Fast Turn Mode Enable. When this bit is set, the HILO bit determines whether the device receives data transmitted 1MHz
above the RX Synthesizer frequency or 1 MHz below the receiver synthesizer frequency. Use of this mode allows for very fast
turn-around, because the same synthesizer frequency may be used for both transmit and receive, thus eliminating the synthe-
sizer resettling period between transmit and receive. Note that when this bit is set, and the HILO bit is cleared, received data
bits are automatically inverted to compensate for the inversion of data received on the “image” frequency. Typical applications
will set this bit during initialization.
Bit 1 Overwrite Enable. When this bit is set, if an SOP is detected while the receive buffer is not empty, then the existing contents of
receive buffer are lost, and the new packet is loaded into the receive buffer. When this bit is set, the RXOW IRQ is enabled. If
this bit is cleared, then the receive buffer may not be over-written by a new packet, and whenever the receive buffer is not
empty SOP conditions are ignored, and it is not possible to receive data until the previously received packet has been com-
pletely read from the receive buffer.
Bit 0 Valid Flag Enable. When this bit is set, the receive buffer can store up to 8 bytes of data interleaved with valids (data0, valids0,
data1, valids1,...). Typically, this bit is set only when interoperability with first generation devices is desired. See
RX_BUFFER_ADR for more detail.
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