CYP RXC User Manual download pdf (Page 28)

CYRF6936

Document #: 38-16015 Rev. *F Page 28 of 39

Mnemonic ANALOG_CTRL_ADR

Address 0x39

Bit 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

Function RSVD RSVD RSVD RSVD RSVD RSVD RX INV ALL SLOW

This register provides the ability to override some automatic features of the device.

Bits 7:2 Reserved. Must be zero.

Bit 1 Receive Invert. When set, the incoming receive data is inverted. Firmware MUST set this bit when interoperability with first gen-

eration devices is desired.

Bit 0 All Slow. When set, the synth settling time for all channels is the same as for slow channels. It is recommended that firmware

set this bit when using GFSK data rate mode.

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CYP RXC User Manual Page 28