CYRF6936
Document #: 38-16015 Rev. *F Page 19 of 39
Mnemonic PWR_CTRL_ADR
Address 0x0B
Bit 7 6 5 4 3 2 1 0
Default 1 0 1 - 0 0 0 0
Read/Write R/W R/W R/W - R/W R/W R/W R/W
Function PMU EN LVIRQ EN PMU SEN Not Used LVI TH PMU OUTV
Bit 7 Power Management Unit (PMU) Enable. Setting this bit enables the PMU. When the PMU is disabled, or if the PMU is enabled
and the V
BAT
voltage is above the value set in Bits 1:0 of this register, the V
REG
pin is internally connected to the V
BAT
pin. if the
PMU is enabled and the V
BAT
voltage is below the value set by PMU OUTV, then the PMU will boost the V
REG
pin to a voltage
not less than the value set by PMU OUTV.
Bit 6 Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the V
BAT
voltage
falls below the threshold set by LVI TH, then a low voltage interrupt will be generated. The LVI is not available when the device
is in sleep mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled.
Bit 5 PMU Sleep Mode Enable. If this bit is set, the PMU will continue to operate normally when the device is in sleep mode. If this bit
is not set, then the PMU is disabled when the device is in sleep mode. In this case, if V
BAT
is below the PMU OUTV voltage and
PMU EN is set, when the device enters sleep mode the V
REG
voltage falls to the V
BAT
voltage as the V
REG
capacitors dis-
charge.
Bits 3:2 Low Voltage Interrupt Threshold. This field sets the voltage on V
BAT
at which the LVI is triggered. 11 = 1.8V; 10 = 2.0V;
01 = 2.2V; 00 = PMU OUTV voltage.
Bits 1:0 PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V; 10 = 2.5V; 01 = 2.6V; 00 = 2.7V. When
the PMU is active, the voltage output by the PMU on V
REG
will never be less than this voltage provided that the total load on the
V
REG
pin is less than the specified maximum value, and the voltage in V
BAT
is greater than the specified minimum value.
Mnemonic XTAL_CTRL_ADR
Address 0x0C
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 - - 1 0 0
Read/Write R/W R/W R/W - - R/W R/W R/W
Function XOUT FN XSIRQ EN Not Used Not Used FREQ
Bits 7:6 XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT
FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire
mode then the MISO pin will output a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to
GPIO mode, and set the GPIO state in IO_CFG_ADR.
Bit 5 Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event
when the crystal has stabilized after the device has woken from sleep mode. This event is cleared by writing zero to this bit.
Bits 2:0 XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz; 1 = 6 MHz,
2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
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