CYRF6936
Document #: 38-16015 Rev. *F Page 26 of 39
Mnemonic TX_OVERRIDE_ADR
Address 0x1F
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Function ACK TX FRC PRE RSVD MAN TXACK OVRD ACK DIS TXCRC RSVD TX INV
This register provides the ability to over-ride some automatic features of the device.
Bit 7 When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the
given channel when automatically entering transmit mode.
Bit 6 Force Preamble. When this bit is set, the device will transmit a continuous repetition of the preamble pattern (see
PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures. Firmware should set bit
RST of MODE_OVERRIDE_ADR to exit this mode.
Bit 5 Reserved. Must be zero.
Bit 4 Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set.
Bit 3 ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet.
Bit 2 Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets.
Bit 1 Reserved. Must be zero.
Bit 0 TX Data Invert. When this bit is set the transmit bitstream is inverted.
Mnemonic XTAL_CFG_ADR
Address 0x26
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Function RSVD RSVD RSVD RSVD START DLY RSVD RSVD RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:4 Reserved. Must be zero.
Bit 3 Crystal Startup Delay. Setting this bit, sets the crystal startup delay to 150uSec to handle warm restarts of the crystal. Firmware
MUST set this bit during initialization.
Bits 2:0 Reserved. Must be zero.
Mnemonic CLK_OVERRIDE_ADR
Address 0x27
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Function RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:2 Reserved. Must be zero.
Bit 1 Force Receive Clock. Streaming applications MUST set this bit during receive mode, otherwise this bit is cleared.
Bit 0 Reserved. Must be zero.
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